Low dropout voltage regulators (LDOs) are voltage regulators that may operate with a small input-output differential voltage while maintaining a substantially constant output voltage. One performance measure of LDOs is power supply rejection ratio (PSRR) which measures how well an LDO rejects noise contained in the input voltage. Higher PSRR means that the output voltage is less sensitive to the noise component contained in the input voltage and is thus more desirable.
FIG. 1 illustrates an LDO that is commonly known in the art. The LDO as shown in FIG. 1 includes an amplifier 12, a PMOS 14, resistors 16, 18, and a capacitor 10 for load compensation. The amplifier 12 includes a first input coupled to a reference voltage VREF and a second input for receiving a feedback voltage VFB. An output of the amplifier 12 is coupled to a gate of the PMOS 14. A source of the PMOS 14 is coupled to a voltage source VDD, and a drain of the PMOS 14 is coupled to the serially-connected resistors 16, 18. The serially-connected resistors 16, 18 form a voltage divider which provides the feedback voltage VFB to the second input of the amplifier 12. The drain of PMOS 14 provides an output voltage VOUT to capacitor 10. The output voltage VOUT may be divided by the voltage divider formed by resistors 16, 18 to produce the feedback voltage VFB proportional to VOUT, where the proportional ratio is determined by the resistance values of resistors 16, 18. The amplifier 12 minimizes the voltage difference between VREF and VFB so that voltage fluctuations in VOUT caused by noise in VDD may be mitigated through the feedback loop and VOUT may be kept substantially free of the noise component in VDD. However, the LDO as shown in FIG. 1 may have certain drawbacks. For example, the high frequency component in the input may be passed to the output of the LDO directly because of the limited bandwidth of the LDO. When the feedback loop is open, the noise component in VDD may be directly passed to VOUT, and thus PSRR suffers. When VDD is much higher than VOUT (VDD>>VOUT), the output PMOS works in the saturation mode, and PSRR is usually very high in low-to-mid frequency range (F<Gain Bandwidth (GBW)) due to the gain of the LDO. However, when the voltage dropout is low (VDD−VOUT≦100 mV) and the output current IOUT is high or at maximum, the PSRR is usually low because the output transistor 14 may be transitioned from a saturation mode to a triode mode due to the low differential voltage from VDD to VOUT. This transition from the saturation mode to the triode mode may cause cause LDO gain loss and worsen PSRR at output.
FIG. 2 illustrates another LDO that is known in the art. The LDO as shown in FIG. 2 includes an NMOS 15 and gate-to-gate connected PMOS 20, 22 that form a current mirror. The sources of PMOS 20, 22 are coupled to the input voltage VDD. Thus, the current that flows through the output PMOS 22 may mirror the current that flows through the mirror PMOS 20. However, when the voltage drop is low (or VDD−VOUT≦100 mV), the output PMOS 22 may be transitioned from a saturation mode to a triode mode while the mirror PMOS 20 is still in the saturation mode. This mode imbalance between the output PMOS 20 and mirror PMOS 22 for low dropout voltages may cause low PSRR. Further, another drawback of the circuit as shown in FIG. 2 is that the gate of the output PMOS 22 is not pulled down close to ground, which results in the need for a much larger PMOS 22 for a given voltage dropout. A large PMOS 22 occupies more circuit area and consumes more power.
FIG. 3 illustrates another LDO that is similar to the LDO as shown in FIG. 2. Compared to FIG. 2, the LDO as shown in FIG. 3 further includes gate-to-gate connected PMOS 24, 26, and a current source 28, all of which may allow the gate of the output PMOS 22 to be pulled close to ground. However, the LDO as shown in FIG. 3 still suffers the same drawback of imbalanced current mirror at low dropout as the LDO of FIG. 2. Further, the LDO as shown in FIG. 3 may be difficult to stabilize during a transition from the triode mode to the saturation mode.